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HMC920LP5E
v07.1013
ACTIVE BIAS CONTROLLER
Low Voltage Linear Regulator (VDIG)
Place the R1 and R3 resistor as close as possible to the VDIG FB pin.
To ensure stable operation of VDIG, bypass VDIG to AGND with a 10礔 tantalum capacitor (with R
ESR
> 200m&)
under full-load conditions.
The HMC920LP5E requires a low voltage bias rail (3.3V to 5V) for internal circuitry. An internal linear regulator
produces a preset 3.5V low-current VDIG output. VDIG powers the internal logic circuitry, oscillator and the control of
the negative charge pump. VDIG supplies a maximum of 30mA current and therefore it is recommended for external
use only for light loading.
If needed the VDIG output can be adjusted externally through R1 and R3, to a maximum of 5V. To adjust the VDIG
value, set R1 to 10k& and determine the value of R3 using the equation (1):
If a 3.3V/5V supply is already available externally, internal low-voltage regulator can be disabled to increase the overall
system efficiency. To deactivate the internal low-voltage regulator, connect a 0Ohm resistor on R3 (depopulate R1),
and connect the external supply to VDIG pin. The typical current consumption from VDIG pin is less than 5mA. The
correct power up sequence is GND, VDD, VDIG, VNEG, and signal pins.
Reference (BGCAP)
The HMC920LP5E employs two reference voltage generators. The first reference voltage generates 2.5V accurate
to ?% over temperature, supply, and load variations.. This reference voltage generator is used to bias VDIG LDO.
A second reference generator generates a stable 2V reference accurate to ?% over temperature, supply, and load
variations. In order to decrease noise, it is recommended to bypass BGCAP to AGND with a 0.1糉 or greater ceramic
capacitor, as close as possible to the BGCAP pin as possible.
R3 = x (VDIG - 2.5) (1)
R1
2.5
Figure 1. Low Voltage Linear Regulator (VDIG) Block Diagram